Onsemi Unveils Embedded Power Platform Chip Architecture to Boost Power Density for AI Data Centers

US chipmaker Onsemi has introduced a new chip architecture designed to address one of the most pressing constraints facing AI data centers: the ability to pack ever-greater amounts of power into a fixed rack footprint. The Embedded Power Platform, or EPP, uses the silicon wafer itself as an embedded package, integrating electrical, mechanical, and thermal design to help customers achieve higher power density and improve AI system performance.

The announcement comes as rack power demands are rising at a pace that traditional packaging approaches may struggle to support. Dinesh Ramanathan, senior vice president of corporate strategy at Onsemi, said racks today are roughly 60kW, but that figure is expected to climb to 200kW within the next two years and reach 1MW by the end of the decade. "The space in the rack isn't changing, but the amount of power that rack is going to end up consuming is increasing by a dramatic amount," Ramanathan said. "So, if you have to support that and make sure that data center rack can consume the 1MW and give us the kind of AI capabilities that we're looking for, then we have to drive towards an increase in power density across that entire rack. If we can't increase the power density across the entire rack, we'll never be able to reach 1MW."

At a basic level, EPP works by creating a cavity inside a silicon wafer and placing the die into that cavity. Using the wafer as the package allows silicon, silicon carbide, and vertical gallium nitride to be seamlessly interconnected within a highly integrated wafer-level architecture. The platform also enables multiple devices, including FETs, drivers, and controllers, to be embedded together in a single package that has been co-optimized for electrical, thermal, and mechanical performance. According to Onsemi, an early EPP-based solid-state circuit-breaker design was found to be approximately 50 percent smaller and 20 percent cooler than existing designs.

The platform leverages Onsemi's standard 12-inch silicon wafer manufacturing capabilities, including mature semiconductor design tools, wafer-level manufacturing, advanced simulation capabilities, and power system integration. "By reducing packaging overhead and using the full EPP footprint to conduct heat, EPP can support more compact power systems, improve thermal management and enable greater power density in AI infrastructure," the company said in a statement.

Onsemi has already partnered with Subaru for the deployment of EPP, with the automaker set to gain early access to engineering samples, simulation models, and technical expertise. Ramanathan said the chipmaker is also partnering with both an industrial company and an AI data center company, though he said Onsemi was not currently in a position to name them. "We have shown [these customers] what the technology can do, and we're working towards getting this product into revenue in the 2027 time frame, so we're sampling our customers this year," Ramanathan said. "The expectation is that in Q1, this technology will be qualified, and then made generally available for any of our customers to take to market."

The introduction of EPP underscores a broader shift in the semiconductor and data center industries, where power delivery and thermal management are increasingly viewed as critical bottlenecks to scaling AI infrastructure. As rack densities climb toward 1MW, chipmakers are under pressure to deliver packaging innovations that can keep pace with the power demands of next-generation AI accelerators and high-performance computing systems. Onsemi's wafer-level approach represents one attempt to address that challenge by embedding power devices directly into the silicon package rather than relying on conventional discrete packaging methods.